1. Field of the Invention
The present invention relates to a current switching type logic circuit such as an emitter-coupled logic circuit, a source-coupled logic circuit or a current mode logic circuit.
2. Description of the Background Art
FIG. 17 is a circuit diagram showing the structure of a conventional emitter-coupled logic circuit 31. Referring to FIG. 17, this emitter-coupled logic circuit 31 includes an input terminal Vi1, a reference potential terminal Vbb1, first and second output terminals Vo1 and Vo2, and first and second power supply terminals Vcc and Vee. A binary logic signal having logical high and low levels is inputted in the input terminal Vi1. A voltage providing a threshold value of the logic of the input logic signal is applied to the reference potential terminal Vbb1. A first power supply potential as one operation power supply potential is applied to the first power supply terminal Vcc, while a second power supply potential, as another operation power supply potential, which is lower than the first power supply potential is applied to the second power supply terminal Vee. Load capacitances such as the input capacitance of a next stage gate and an interconnection line capacitances are associated with the first and second output terminals Vo1 and Vo2.
The emitter-coupled logic circuit 31 further includes a current switching circuit 31a and an emitter-follower circuit 31b. The current switching circuit 31a includes an input transistor Q31, a reference transistor Q32, resistances R31 and R32, and a current source I31. The transistors Q31 and Q32 have bases which are connected to the input terminal Vi1 and the reference potential terminal Vbb1 respectively, collectors which are connected to the first power supply terminal Vcc through the resistances R31 and R32 respectively, and emitters which are connected together to the second power supply terminal Vee through the current source I31.
The emitter-follower circuit 31b includes pull-up transistors Q33 and Q34 and current sources I32 and I33. The pull-up transistors Q33 and Q34 have bases which are connected to the collectors of the transistors Q31 and Q32 respectively, collectors which are connected to the first power supply terminal Vcc, and emitters which are connected to the first and second output terminals Vo1 and Vo2 respectively as well as to the second power supply terminal Vee through the current sources I32 and I33 respectively.
The operation is now described. When the input logic signal is changed from a logical low level to a logical high level, the transistors Q31 and Q32 enter conducting and cutoff states respectively. Therefore, most of a switching current Is of the current source I31 flows in the resistance R31 through the transistor Q31. The base potential of the transistor Q33 is reduced by a voltage drop in the resistance R31, so that the transistor Q33 enters a cutoff, or a weak off state. On the other hand, the collector voltage of the transistor Q32, i.e., the base voltage of the transistor Q34 is increased substantially up to the potential of the first power supply terminal Vcc, whereby the transistor Q34 enters a conducting state. Thus, charges of the load capacitance which is connected to the output terminal Vo1 are extracted by the current source I32, whereby the voltage of the output terminal Vo1 is changed from a logical high level to a logical low level. On the other hand, the load capacitance which is connected to the output terminal Vo2 is charged through the transistor Q34, whereby the voltage of the output terminal Vo2 is changed from a logical low level to a logical high level.
In this emitter-coupled logic circuit 31, the speed of response is decreased by the load capacitances. In order to attain a speed increase, therefore, it is necessary to increase emitter-follower currents Ie1 and Ie2 flowing in the current sources I32 and I33, and hence power consumption is disadvantageously increased. Further, the emitter-follower currents Ie1 and Ie2 continuously flow when the outputs remain unchanged, leading to inferior current efficiency.
Such disadvantages may be overcome by a circuit which is described in ISSCC (International Solid State Circuits Conference) '89, pp. 224-225, for example. FIG. 18 is a circuit diagram showing the structure of an emitter-coupled logic circuit 32 which is described in this article. Referring to FIG. 18, this emitter-coupled logic circuit 32 includes an input terminal Vi1, a reference potential terminal Vbb1, an output terminal Vo1 and first and second power supply terminals Vcc and Vee. The emitter-coupled logic circuit 32 further includes a current switching circuit 31a which is identical in structure to that shown in FIG. 17, and an emitter-follower circuit 32b.
The emitter-follower circuit 32b includes a capacitive element C31, diodes D31 and D32, a current source I34, a pull-up transistor Q33, a pull-down transistor Q35, and a resistance 33. The diodes D31 and D32 and the current source I34 are connected in series between the first and second power supply terminals Vcc and Vee, to form a bias circuit. The capacitive element C31 is connected between the collector of a reference transistor Q32 and a node N31. The pull-up transistor Q33 has a base which is connected to the collector of an input transistor Q31, a collector which is connected to the first power supply terminal Vcc, and an emitter which is connected to the output terminal Vo1. The pull-down transistor Q35 has a base which is connected to the node N31, a collector which is connected to the output terminal Vo1, and an emitter which is connected to the second power supply terminal Vee through the resistance R33.
The operation is now described. When an input logic signal is changed from a logical low level to a logical high level, the transistors Q31 and Q32 enter conducting and cutoff states respectively. Therefore, most of a switching current Is flows in a resistance R31 through the transistor Q31, and the base potential of the pull-up transistor Q33 is reduced due to a voltage drop by the resistance R31 so that the pull-up transistor Q33 enters a cutoff state. On the other hand, the collector voltage of the transistor Q32 is increased substantially up to the potential of the first power supply terminal Vcc and the base potential of the pull-down transistor Q35 is increased through capacitive coupling by the capacitive element C31, whereby an emitter-follower current Ie1 is increased. Thus, charges of a load capacitance CL1 which is connected to the output terminal Vo1 are rapidly extracted and a signal at the output terminal Vo1 is changed from a logical high level to a logical low level.
In this emitter-coupled logic circuit 32, the emitter-follower current Ie1 is set at a small value when the logical level of the input logic signal remains unchanged while the emitter-follower current Ie1 is increased only when the logical level of the input logic signal is changed to fall the output signal. Thus, it may be possible to reduce power consumption while maintaining a high-speed operation.
However, it is necessary to change the potential of the node N31 at a high speed by the capacitive coupling of the capacitive element C31. In this case, the capacitive element C31 requires a capacitance value of about several pF, resulting in increase in area, and the number of steps for formation of the capacitive element C31 is increased. Further, only one of inverted and non-inverted outputs can be taken out and hence it is impossible to accommodate complementary signal outputs.
An exemplary emitter-coupled logic circuit which can provide complementary outputs is illustrated in FIG. 5(b) of Japanese Patent Laying-Open No. 4-364607 (1992). FIG. 19 is a circuit diagram showing the structure of an emitter-coupled logic circuit 33 shown in this document. Referring to FIG. 19, this emitter-coupled logic circuit 33 includes an input terminal Vi1, first and second reference potential terminals Vbb1 and Vbb2, first and second output terminals Vo1 and Vo2, and first and second power supply terminals Vcc and Vee. An input threshold voltage for a pull-down transistor Q35 is applied to the second reference potential terminal Vbb2. The emitter-coupled logic circuit 33 further includes a current switching circuit 31a which is identical in structure to that shown in FIG. 17, and an emitter-follower circuit 33b.
The emitter-follower circuit 33b includes pull-up transistors Q33 and Q34, pull-down transistors Q35 and Q36, and a current source I35. The pull-up transistors Q33 and Q34 have bases which are connected to collectors of transistors Q31 and Q32 respectively, collectors which are connected to the first power supply terminal Vcc, and emitters which are connected to the first and second output terminals Vo1 and Vo2 respectively. The pull-down transistors Q35 and Q36 have bases which are connected to emitters of the transistors Q31 and Q32 and the second reference potential terminal Vbb respectively, collectors which are connected to the first and second output terminals Vo1 and Vo2 respectively, and emitters which are connected together to the second power supply terminal Vee through the current source I35.
When an input logic signal Vi1 is changed from a logical low level to a logical high level, the base potential of the pull-up transistor Q33 drops and that of the pull-up transistor Q34 is increased as hereinabove described. The base potential of the pull-down transistor Q35 is increased following the signal supplied to the input terminal Vi1 by an emitter-follower operation of the transistor Q31. Therefore, the pull-up transistor Q33 enters a cutoff state and the pull-down transistor Q35 enters a conducting state, whereby a signal at the first output terminal Vo1 is changed from a logical high level to a logical low level. Further, the pull-up transistor Q34 enters a conducting state and the pull-down transistor Q36 enters a cutoff state, whereby a signal at the second output terminal Vo2 is changed from a logical low level to a logical high level.
This emitter-coupled logic circuit 33 has such disadvantages that the second reference potential terminal Vbb2 is additionally required and the amplitude of the potential which is applied to the base of the pull-down transistor Q35 is substantially halved as compared with the logic amplitude of the input logic signal since a logical high level thereof is Vi1(H)-VBE and a logical low level thereof is Vbb1-VBE, where Vi1(H) represents a logical high level voltage of the input logic signal at the terminal Vi1 and VBE represents the base-to-emitter voltage of the transistors Q31 and Q32.
Another exemplary conventional circuit which can provide complementary outputs is described in Japanese Patent Publication No. 1-54890 (1989). FIG. 20 is a circuit diagram showing the structure of an emitter-coupled logic circuit 34 which is described in this document. Referring to FIG. 20, this emitter-coupled logic circuit 34 includes an input terminal Vi1, a first reference potential terminal Vbb1, an output terminal Vo1, and first and second power supply terminals Vcc and Vee. Further, the emitter-coupled logic circuit 34 includes a current switching circuit 31a which is identical in structure to that shown in FIG. 17, and an emitter-follower circuit 34b.
The emitter-follower circuit 34b includes an NPN multi-emitter transistor Q37 having first and second emitters, a Schottky diode SD31, a resistance R34 and a PNP transistor QP31. The multi-emitter transistor Q37 has a base which is connected to the collector of a transistor Q31, a collector which is connected to the first power supply terminal Vcc, the first emitter which is connected to the second power supply terminal Vee through the Schottky diode SD31 and the resistance R34, and the second emitter which is connected to the output terminal Vo1. The PNP transistor QP31 has a base which is connected to a node between the Schottky diode SD31 and the resistance R34, an emitter which is connected to the output terminal Vo1, and a collector which is connected to the second power supply terminal Vee.
The operation is now described. When an input logic signal is at a logical low level and the transistor Q31 is in a cutoff state and transistors Q32 and Q37 are responsively in conducting states respectively, a voltage which is applied across the Schottky diode SD1 is smaller than the base-to-emitter voltage of the PNP transistor QP31, whereby the PNP transistor QP31 is in a cutoff state. Therefore, a load capacitance CL1 is charged through the multi-emitter transistor Q37, and the potential at the output terminal Vo1 attains a logical high level.
When the input logic signal is changed from the logical low level to a logical high level and responsively the transistor Q31 enters a conducting state and the transistors Q32 and Q37 enter cutoff states, the sum of the voltage across the first and second emitters of the multi-emitter transistor Q37 and that applied across the Schottky diode SD31 exceeds the base-to-emitter voltage of the PNP transistor QP31, whereby the PNP transistor QP31 enters a conducting state. Therefore, charges of the load capacitance CL1 are rapidly discharged through the PNP transistor QP31, and a voltage at the output terminal Vo1 is changed to a logical low level.
In this emitter-coupled logic circuit 34, the high-speed PNP transistor QP31 of a different conductivity type is required and hence the manufacturing process cost is increased. In addition the Schottky diode SD31 which is different from a PN diode is required and hence the process is complicated and the manufacturing cost is increased.